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The I²C bus and the SMBus are popular 2-wire buses that areessentially compatible with each other.

Minimum Clock SpeedDC10KHz
Maximum Clock Speed100kHz (400kHz and 2MHz also available)100kHz
VHIGH0.7 × VDD, 3.0V Fixed2.1V
VLOW0.3 × VDD, 1.5V Fixed0.8V
Max I3mA350µA
Clock NomenclatureSCLSMBCLK
Data NomenclatureSDASMBDAT
General CallYesYes

SMBus and I2C

Detailed reference: the difference between SMBus and I2C

SMbus It was first proposed by Intel. It is now managed by SBS to maintain this specification. This specification is simplified with the I2C of Philips. SMbus is a confluence of two signals. It is a slower device on the system.Communication with power management devices enables the system to obtain the manufacturer, model, control information, error message and status of these devices.

operating frequency”

 In terms of operating frequency, I2C is quite abundant in this aspect, the lowest frequency can be 0Hz (DC state, wait for time pause), high to 100kHz (Standard Mode), 400kHz (Fast Mode), and 3.4MHz (High S)Peed Mode), the relative SMBus is very limited, the slowest is not slower than 10kHz, the fastest is not fast than 100kHz. Obviously, the frequency of intersection between I2C and SMBus is 10kHz~100kHz.

data retention time”

After the request of the speed transmission, there is a request for Data Hold Time. After the SMBus stipulates that the SMBCLK line is down, the data on the SMBDAT must continue to retain the 300nS, but I2C does not have the same mandatory requirements for this. Allied,SMBus is also required for the recovery time (Timeout) after the interface is reset (Reset). In general, it is 35mS, and I2C has no constraints. It can extend the time arbitrarily. The same SMBus also requires both at the main control (Master) or the controlled end (S).Lave), the longest duration of the time pulse at the Lo quasi position should not exceed the limit, so as to avoid the time sequence derailment at both ends of the transceiver (losing synchronization, resulting in subsequent misoperation) because of the long time in the Lo quasi position.

current limit

Since the current is limited, it is also easy to deduce the range requirements for the resistance to the lifting resistance. When the I2C is at the 5V Vdd, it is larger than the 1.6K ohm, and when the 3V Vdd is larger than 1K ohm, the similar SMBus is larger than the 5V Vdd.When 3V Vdd is larger than 8.5k ohm, this definition is not unbreakable. In general practice, 2.4k~3.9k Ohm Category can also be used on SMBus.

capacitance limit

Furthermore, the restriction is related, I2C has the limit of line capacitance, but there is no SMBus, but there is a similar matching specification, that is, the current limit of the quasi bit pull down. When the open set foot of the SMBus is connected to the gate to make the line grounded, the current that flows through the ground must not be higher than the 350uA, and the other is pulled up.Current (that is the same open collector pole open circuit) is also standardized, the minimum is not less than 100uA, the highest is not broken 350uA.


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